Mr. Rakshith Saligram, a trailblazing researcher in the field of VLSI, is celebrated for his groundbreaking work in cryogenic CMOS circuits at the Georgia Institute of Technology. 🌐 With a stellar academic background, including a PhD from Georgia Tech and an MS Honors from USC, he has consistently maintained top-tier performance. 🎓 His journey began at BMSCollege of Engineering, where he excelled in Electronics and Communication Engineering, culminating in a thesis on fault-tolerant ALUs. 💡 Rakshith’s expertise extends to cryogenic memory design, thermal analysis, and high-speed IO design, evident through his involvement in projects with Microsoft, Samsung, and more. 🚀 Notable contributions include DARPALTLT for dense cryogenic memories and DARPATHERMONAT for self-heating analysis. As a lecturer and course development assistant at USC, he showcased his commitment to education. 📚 Rakshith’s industry experience spans ARM Inc. and Intel Corporation, where he played a pivotal role in the development of Intel’s GFx processors. His passion for innovation and interdisciplinary collaboration continues to drive advancements in VLSI and beyond. 👨💻🔬
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Education:
Rakshith Saligram, an accomplished researcher, pursues his PhD at the Georgia Institute of Technology under the guidance of advisor Arijit Raychowdhury, showcasing academic excellence with a perfect 4.0 GPA. 🎓 His journey began with a stellar thesis on designing fault-tolerant ALUs during his Electronics and Communication Engineering studies at BMSCollegeofEngineering. 🌐 Further enriching his knowledge, Rakshith earned an MS Honors in VLSI Design and Computer Engineering at the University of Southern California, achieving an impressive 3.87 GPA. 🚀 His commitment to academic and research excellence continues to propel him as a distinguished scholar in the field. 👨💻✨
Experience:
Rakshith Saligram, a dedicated Graduate Research Assistant at the Integrated Circuits and Systems Research Lab, Georgia Institute of Technology, is at the forefront of cutting-edge technology. 🌐 Specializing in Cryogenic CMOS Circuits, VLSI, Thermal Analysis, and High-Speed IO Design, he contributes significantly to projects like DARPALTLT, DARPATHERMONAT, Microsoft HPC, Samsung-GRO, and ASCENT, showcasing his expertise in modeling, designing, and analyzing advanced technologies. 🚀 Rakshith’s passion for education is evident through his role as a Course Development Assistant at USC, where he enhanced the MOS VLSI Circuit Design curriculum. As a lecturer at BMSCollegeofEngineering, he instructed and coordinated, leaving an indelible mark. 📚 In industry, his internships at IMEC USA Nanoelectronic Design Center, ARM Inc., and Intel Corporation highlight his impactful work in superconducting research, ARM core benchmarking, and graphics hardware engineering. 👨💻✨
Award & Honors:
Rakshith Saligram, a distinguished professional and academic, has garnered numerous accolades for his outstanding contributions. In the corporate realm, his visionary leadership earned him team recognitions for pioneering partition execution strategies, achieving LV closure, and resolving complex issues in chip design. 🏆 His journey also includes significant milestones in academia, marked by being a finalist in the Qualcomm Innovation Fellowship and receiving the GT-ORNL PhD Seed Research Grant Award for Cryogenic CMOS interface circuits. 🎓 Notably, his Best Paper Award at the IEEE International Conference and recognition by the Ministry of Human Resource Development showcase his excellence in research and dedication to advancing technology. 👨💻✨
Publications:
- Design of High-Speed Low-Power Multiplier Using Reversible Logic: A Vedic Mathematical Approach”
- Authors: TR Rakshith, R Saligram
- Year: 2013
- Citation: 77 citations
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- “Novel Code Converter Employing Reversible Logic”
- Authors: R Saligram, TR Rakshith
- Year: 2012
- Citation: 39 citations
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- “Optimized Reversible Vedic Multipliers for High-Speed Low-Power Operations”
- Authors: R Saligram, TR Rakshith
- Year: 2013
- Citation: 34 citations
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- “Design of Reversible Multipliers for Linear Filtering Applications in DSP”
- Authors: R Saligram, TR Rakshith
- Year: 2012
- Citation: 34 citations
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- “CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications”
- Authors: R Saligram, S Datta, A Raychowdhury
- Year: 2021
- Citation: 22 citations
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- “Design of Parity Preserving Logic-Based Fault Tolerant Reversible Arithmetic Logic Unit”
- Authors: R Saligram, SS Hegde, SA Kulkarni, HR Bhagyalakshmi, MK Venkatesha
- Year: 2013
- Citation: 21 citations
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- “Parity Preserving Logic-Based Fault Tolerant Reversible ALU”
- Authors: TR Rakshith, R Saligram
- Year: 2013
- Citation: 18 citations
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- “Design of Fault Tolerant Reversible Multiplexer Based Multi-Boolean Function Generator Using Parity Preserving Gates”
- Authors: R Saligram, SS Hegde, SA Kulkarni, HR Bhagyalakshmi, MK Venkatesha
- Year: 2013
- Citation: 17 citations
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- “A 64-Bit Arm CPU at Cryogenic Temperatures: Design Technology Co-Optimization for Power and Performance”
- Authors: R Saligram, D Prasad, D Pietromonaco, A Raychowdhury, B Cline
- Year: 2021
- Citation: 15 citations
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- “2021 IEEE Int. Electron Devices Meeting IEDM”
- Authors: W Wei, W Zhang, L Tai, G Zhao, P Sang, Q Wang, F Chen, M Tang, …
- Year: 2021
- Citation: 13 citations
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